4502 Addressing mode: Zeropage/Relative -- d,rr (BBR0,BBR1,BBR2,BBR3,BBR4,BBR5,BBR6,BBR7,BBS0,BBS1,BBS2,BBS3,BBS4,BBS5,BBS6,BBS7) (3 bytes) (3,4 and 6 cycles) TODO - Info missing! +---------------+------------------+-----------------------+----------+ | Cycle | Address Bus | Data Bus |Read/Write| +---------------+------------------+-----------------------+----------+ | 1 | PBR,PC | Op Code | R | | 2 | PBR,PC+1 | Direct Offset | R | | (2) 2a | PBR,PC+1 | Internal Operation | R | | 3 | PBR,PC+1 | Internal Operation | R | | 4 | 0,D+DO+I | Data Low | R/W | | (1) 4a | 0,D+DO+I+1 | Data High | R/W | +---------------+------------------+-----------------------+----------+ (1) Add 1 cycle for M=0 or X=0 (i.e. 16 bit data). (2) Add 1 cycle for direct register low (DL) not equal 0. See also: Abbreviations