ASLQ Shift Left One Bit (Q pseudo registers) ASLQ Operation: Q <- Q << 1 or M <- M << 1 N V - B D I Z C / . . . . . / / 4510 Versions: +----------------+-----------------------+-----------+---------+----------+ | Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles| +----------------+-----------------------+-----------+---------+----------+ |ZeroPage Quad | ASLQ $FF |$42 $42 $06| 4 | 12dmr | |Accumulator Quad| ASLQ (A) |$42 $42 $0A| 3 | 3 | |Absolute Quad | ASLQ $FFFF |$42 $42 $0E| 5 | 13dmr | |ZeroPage Quad,X | ASLQ $FF,X |$42 $42 $16| 4 | 12dmpr | |Absolute Quad,X | ASLQ $FFFF,X |$42 $42 $1E| 5 | 13dmpr | +----------------+-----------------------+-----------+---------+----------+ d Sub 1 if CPU is at 3.5 MHz m Sub non-bus cycles when at 40 MHz p Add 1 if page boundary is crossed. r Add 1 if clock speed is at 40 MHz