CLI                  CLI Clear interrupt disable bit                  CLI

  Operation: 0 -> I                                     N V - B D I Z C
                                                        . . . . . 0 . .

  +----------------+-----------------------+---------+---------+----------+
  | Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
  +----------------+-----------------------+---------+---------+----------+
  |  Implied       |   CLI                 |   $58   |    1    |    2     |
  +----------------+-----------------------+---------+---------+----------+


 4510 Versions:

  +----------------+-----------------------+---------+---------+----------+
  | Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
  +----------------+-----------------------+---------+---------+----------+
  |  Implied       |   CLI                 |   $58   |    1    |    1s    |
  +----------------+-----------------------+---------+---------+----------+
  s Instruction requires 2 cycles when CPU is run at 1 MHz or 2 MHZ